A circuit analysis and WCCA report is required before spacecraft launch. This is an example of a FPGA 256GB DDR3 memory/telemetry recording board that failed signal integrity tests. A report was written and design changes made.
Extreme fanout simulation with Hyperlynx Line Sim
FPGA pins ’fan out’to DDR3 address lines, each pin driving 84 devices, creating an extremely long rise time on the address lines.
Address setup and hold margin
Circuit does meet the signal requirements at 18 MHz, for 1GHz DDR3 devices.
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